In the npn (pnp) bipolar transistor, the emitter layer consists of n-type (p-type) semiconducting material that is deposited on top of the epitaxially-grown base structure. The emitter itself is either polycrystalline or monocrystalline. A monocrystalline emitter is preferred from the point of view of device integration because it allows for a reduction of parasitic resistance and enables band gap engineering of the emitter stack in the perspective of optimization of the transistor performances. In both cases, high dopant concentration (above 1×1020 atoms/cm3) is desired in order to achieve a low-resistance emitter layer.
Nowadays the fabrication of a bipolar transistor is performed in a BiCMOS process flow, which means that the thermal anneal that drives the dopants from the emitter layer into the base layer also serves as junction activation anneal for the CMOS part of the device. This step, which consists of a spike anneal occurring after the deposition of the emitter layer, is usually fixed by the optimization of the CMOS part of the process flow and provides a relatively high thermal budget which might adversely impact the bipolar device characteristics.